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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Ball Descriptions
Ball Descriptions
Table 1:
VFBGA
VFBGA Ball Descriptions
Assignment
G2, H1, D3, E4,
F4, F3, G4, G3,
H5, H4, H3, H2,
D4, C4, C3, B4,
Symbol
A[19:0]
Type
Input
Description
Address inputs: Inputs for addresses during READ and WRITE operations.
Addresses are internally latched during READ and WRITE cycles. The address lines
are also used to define the value to be loaded into the bus configuration register
or the refresh configuration register.
B3, A5, A4, A3
J2
CLK
Input
Clock: Synchronizes the memory to the system operating frequency during
synchronous operations. When configured for synchronous operation, the address
is latched on the first rising CLK edge when ADV# is active. CLK is static LOW or
HIGH during asynchronous access READ and WRITE operations and during PAGE
READ ACCESS operations.
J3
ADV#
Input
Address valid: Indicates that a valid address is present on the address inputs.
Addresses can be latched on the rising edge of ADV# during asynchronous READ
and WRITE operations. ADV# can be held LOW during asynchronous READ and
WRITE operations.
A6
CRE
Input
Configuration register enable: When CRE is HIGH, WRITE operations load the
refresh configuration register or bus configuration register.
B5
CE#
Input
Chip enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby or deep power-down mode.
A2
OE#
Input
Output enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
G5
WE#
Input
Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle
is a WRITE to either a configuration register or to the memory array.
A1
B2
G1, F1, F2, E2,
D2, C2, C1, B1,
LB#
UB#
DQ[15:0]
Input
Input
Input/
Output
Lower byte enable: DQ[7:0].
Upper byte enable: DQ[15:8].
Data inputs/outputs.
G6, F6, F5, E5,
D5, C6, C5, B6
J1
WAIT
Output
Wait: Provides data-valid feedback during burst READ and WRITE operations. The
signal is gated by CE#. WAIT is used to arbitrate collisions between REFRESH and
READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary.
WAIT is also used to mask the delay associated with opening a new internal page.
WAIT is asserted and should be ignored during asynchronous and page mode
operations. WAIT is High-Z when CE# is HIGH.
E3, H6, J4, J5, J6
D6
E1
E6
D1
NC
V CC
V CC Q
V SS
V SS Q
–
Supply
Supply
Supply
Supply
Not internally connected.
Device power supply (1.7–1.95V): Power supply for device core operation.
I/O power supply (1.7–3.6V): Power supply for input/output buffers.
V SS must be connected to ground.
V SS Q must be connected to ground.
Note:
The CLK and ADV# inputs can be tied to V SS if the device is always operating in asynchro-
nous or page mode. WAIT will be asserted but should be ignored during asynchronous and
page mode operations.
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2005 Micron Technology, Inc. All rights reserved.
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